The present invention relates to a method and apparatus for controlling the operation of a data processing system and, in particular, for controlling an operand fetch operation therein.
A central processing unit (CPU) in a computer system executes data processing tasks or jobs in response to a series of program instructions and data received from an associated external memory unit. The CPU is provided with an internal memory, often referred to as a general register or plurality of general registers, which are utilized for a variety of data storage functions connected with the transfer of data and instructions between the external memory and the CPU and with the execution of programs by the CPU. One or more of the general registers may be used, for example, to perform the function of an accumulator or an index register at various times during operation of the system.
The general registers are addressable in the same manner as the storage locations of the external memory and data stored in the registers and external memory is accessed through operation of some form of operand fetch routine. Conventional systems fall into two general categories: one type employs the same addresses for the internal register locations and the initial storage locations of the external memory and the other type employs different addresses for these two groups of memory locations.
With the former type of system a standarized instruction format may be employed for the internal and external memories, thereby resulting in a very simple program construction. This type of control system, however, is undesirable for many applications in that, since it is impossible to separately designate the respective internal and external memory regions having common addresses, the portion of the external memory which utilizes addresses identical to those of the internal memory are unavailable for use. On the other hand, in a system using different addresses for the internal and external memories, full utilization of the external memory capacity is permissible since there is no address redundancy. However, a drawback of this system is that it is difficult to standardize the instruction format, whereupon program construction and execution is made more complex.